Ibase MI912 User Manual download pdf (Page 40)

BIOS SETUP

MI912 User’s Manual

Advanced Chipset Features

This Setup menu controls the configuration of the chipset.

Phoenix - AwardBIOS CMOS Setup Utility

Advanced Chipset Features

System BIOS Cacheable

Enabled

ITEM HELP

Memory Hole at 15M-16M

Disabled

PCI Express Root Port Func

Press Enter

** VGA Setting **

PEG/On Chip VGA Control

Auto

PEG Force X1

Disabled

On-Chip Frame Buffer Size

8MB

DVMT Mode

DVMT

DVMT/FIXED memory Size

128MB

SDVO Device Setting

None

SDVO LVDS Protocol

1CH 18bit

SDVO Panel Number

852x480

Boot Display

CRT

Panel Scaling

Auto

Panel Number

1024x768 18 bit SC

LAN PXE Option ROM

All Disable

System BIOS Cacheable

The setting of Enabled allows caching of the system BIOS ROM at

F000h-FFFFFh, resulting in better system performance. However, if any

program writes to this memory area, a system error may result.

Video BIOS Cacheable

The Setting Enabled allows caching of the video BIOS ROM at

C0000h-F7FFFh, resulting in better video performance. However, if any

program writes to this memory area, a system error may result.

Memory Hole At 15M-16M

In order to improve performance, certain space in memory can be

reserved for ISA cards. This memory must be mapped into the memory

space below 16 MB. The choices are Enabled and Disabled.

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Ibase MI912 User Manual Page 40

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